Multiphase clocks with guaranteed non-overlapping clock pulses are required for numerous applications. Examples of such applications are switched-capacitor filters, sigma-delta modulators, clock boosters or charge pumps. Circuits for generating two non-overlapping phases or clock phase pairs have been known for a long time from the prior art.
In individual cases, however, it is necessary to generate three or more clock phases which are interleaved in one another and have a defined position with respect to one another, this also ensuring a selection of a plurality of non-overlapping clock phases.
Varying load conditions constitute a particular problem in the generation of non-overlapping clock phases. Through capacitive loads, in particular, clock phases which do not actually overlap others are shifted in such a way that an overlap nonetheless occurs. A circuit from the prior art for two clock phases is illustrated in FIGS. 1 and 2, the resulting clock phases being illustrated in FIG. 3. The circuit arrangement illustrated in FIG. 1 essentially comprises two NAND elements, the output of which is in each case fed back to an input of the other NAND element.
A clock signal CLKIN is present both at the first NAND element 1 and, via an inverter, at the second NAND element 2. In order to explain the function, it is initially assumed that the second input of the NAND element 1 is at LOW. As long as the clock signal CLKIN remains at low, the output Q2 is HIGH. That input of the second NAND element 2 to which the inverted clock signal is applied is at HIGH at this point in time. The output Q2 is fed back to the second input of the second NAND element 2, as a result of which, at this point in time, a HIGH signal is likewise present there, the output of the second NAND element 2 thus goes to LOW and the output signal Q1 is likewise LOW.
When the clock signal CLKIN then changes to HIGH, the rising edge propagates in the circuit. The first input of the first NAND element thus receives a HIGH signal, so that a HIGH level and a LOW level are present at the inputs. The level at the output thus does not change and the edge cannot continue through the first NAND element 1.
The first input of the second NAND element 2 now receives a LOW signal, however, as a result of which the output jumps from LOW to HIGH and the edge continues. The output Q1, which is now HIGH, is fed back to the second input of the first NAND element 1, as a result of which two HIGH signals are present at the inputs of the first NAND element and, consequently, the output goes to low. Consequently, the edge has now also propagated to the second output Q2. This state is maintained until the level of the clock signal CLKIN changes again.
A falling clock edge continues in the manner described with reference to the rising edge. However, initially only the output signal of the first NAND element 1 changes, while despite different occupancy of the inputs, the output signal of the second NAND element 2 remains the same. Therefore, the level of the output Q2 is the first to change, followed by the level of the output Q1. The signals at the outputs Q1 and and Q2 are thus interleaved in one another. The time interval between state changes at the outputs Q1 and Q2 is determined by the magnitude of the delay times of the logic switching elements, that is to say of the NAND elements in FIG. 1.
The delay times can be precisely defined through the targeted use of additional delay elements.
Such a circuit is shown in FIG. 2. In addition to the NAND elements 1 and 2, a plurality of inverters are connected between the outputs of the NAND elements 1 and 2 and the circuit outputs Q1 and Q2, each inverter having a typical switching time which leads to a delay of the signal. In addition, two further outputs Q1N and Q2N are past out, said further outputs respectively carrying the complementary signal with respect to Q1 and Q2.
The signals generated by such a circuit arrangement are illustrated in FIG. 3. The phases Q1 and Q2 are strictly non-overlapping (positive logic), while the phases Q1N and Q2N are strictly overlapping (positive logic) or likewise non-overlapping (negative logic). The clock gap or non-overlapping time is designated by Tnovl. This clock system with two non-overlapping clock phases is suitable for driving switched-capacitor filters or charge pumps, for example.